In the fabrication of integrated circuits and other electronic devices, multiple layers of conducting, semiconducting, and dielectric materials are deposited onto or removed from a substrate surface. As layers of materials are sequentially deposited onto and removed from the substrate, the uppermost surface of the substrate may become non-planar and require planarization. Planarizing a surface, or “polishing” a surface, is a process where material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials. Planarization also is useful in forming features on a substrate by removing excess deposited material used to fill the features and to provide an even surface for subsequent levels of metallization and processing.
Compositions and methods for planarizing or polishing the surface of a substrate are well known in the art. Chemical-mechanical planarization, or chemical-mechanical polishing (CMP), is a common technique used to planarize substrates. CMP utilizes a chemical composition, known as a CMP composition or more simply as a polishing composition (also referred to as a polishing slurry), for selective removal of material from the substrate. Polishing compositions typically are applied to a substrate by contacting the surface of the substrate with a polishing pad (e.g., polishing cloth or polishing disk) saturated with the polishing composition. The polishing of the substrate typically is further aided by the chemical activity of the polishing composition and/or the mechanical activity of an abrasive suspended in the polishing composition or incorporated into the polishing pad (e.g., fixed abrasive polishing pad).
Substrates that have tungsten features disposed between dielectric features include semiconductor substrates that include tungsten “plug” and “interconnect” structures provided between features of dielectric material. The dielectric material (e.g., a silicon oxide) conforms to the underlying topography of the substrate and as such, the surface of the dielectric material typically is characterized by an uneven combination of raised areas of the dielectric material separated by trenches in the dielectric material. The region of the substrate surface that includes the raised dielectric material and trenches is referred to as a pattern field of the substrate, e.g., as “pattern material,” “pattern oxide,” or “pattern dielectric.”
To produce tungsten “plug” and “interconnect” structures, tungsten is applied over a surface that contains a patterned structure made at least in part from dielectric material. Due to variation in the depth of the trenches, it typically is necessary to deposit an excess of tungsten on top of the substrate to ensure complete filling of all trenches. The excess tungsten is then removed by CMP processing to expose the underlying dielectric layer and to produce a planar surface of the tungsten disposed between the spaces of the dielectric material. The tungsten can be removed in a “polishing” step or a “buffing” step, wherein a suitable tungsten removal rate may be desirable, but wherein other performance requirements (e.g., topography performance) also are important.
The special requirements of tungsten buffing slurries which combine the need for tungsten removal with the removal of other film types, such as dielectric oxide films like silicon oxide, present significant challenges. The topography and throughput needs of advanced tungsten nodes require CMP slurries with a combination of improved topography performance, such as lower erosion of oxide, improved performance with extended overpolishing, and reduced localized erosion phenomena such as edge-over erosion (EOE) in pattern arrays and erosion near isolated lines (sometimes referred to as fanging), without compromising film removal requirements. As suggested by the name, EOE or fanging refers to the local erosion near the edge of a patterned area.
However, known CMP slurries suffer from a number of drawbacks, e.g., slurries with film removal rate capability can suffer from excessive EOE which can cause yield loss. Alternatively, many slurries which can achieve desired topography performance suffer from low film removal rates which increases process times, decreasing device throughput. Moreover, topography performance and defectivity have been identified as gaps in existing silica-based tungsten buffing slurries. Anionic systems can improve defectivity while providing improved colloidal stability for improved shelf-life. However, the use of anionic silicas currently is limited due to a number of factors, for example, aluminium-doped silicas have limited operating formulation space due to pH limitations, attributable to Al-leaching. Also, known slurries formulated with anionic particles like MPS (mercapto-propylsilane sulfonated colloidal silica) are limited due to low film removal rates and poor pattern performance (e.g., high erosion or EOE).
Although EOE phenomena are known in various CMP applications, including silicon, copper, and tungsten CMP, the phenomena are not well understood. U.S. Pat. No. 6,114,248 discloses using reduced levels of colloidal and fumed silicas and increased alkaline chemistry in order to improve EOE in polysilicon polishing. Further, it has been proposed that EOE phenomena in copper CMP can be addressed by modifying electrochemical properties of copper (see, e.g., G. Banerjee and R. L. Rhoades (ECS Transactions, 2008, vol. 13, pp. 1-19)). However, chemical-based solutions to fanging in tungsten polishing applications are not likely to be suitable since tungsten has inherently different electrochemical properties from copper and from silicon. Others have proposed EOE in tungsten CMP can be addressed by modifying mechanical factors (e.g., using small particle colloidal silicas) or processing conditions (e.g., two-step high down force followed by low down-force setting during polishing or reconfiguration of the polishing assembly) (see, e.g., R. Vacassy and Z. Chen, “Edge Over Erosion in Tungsten CMP”, 2006, https://www.researchgate.net/publication/290577656; S. H. Shin et al., Relative Motion and Asymmetry Effect Analyses in Tungsten CMP Process,” http://www.planarization-cmp.org/contents/ICPT/PacRim2005/S5-2.pdf).
However, modifying processing parameters typically is undesirable due to the complex operations involved, possible decreases in throughput due to increased polishing times, and/or result in lack of uniform polishing characteristics which can negatively impact device yield. In addition, Applicants have found that tungsten polishing slurries formulated with small colloidal silica results in a high propensity of EOE phenomena in tungsten polishing applications.
Thus, there remains a need for compositions and methods for chemical-mechanical polishing of substrates that will provide useful removal rates while also providing improved planarization efficiency. The invention provides such polishing compositions and methods. These and other advantages of the invention, as well as additional inventive features, will be apparent from the description of the invention provided herein.